FEATURES
·
50% Duty Cycle Output
Optimized for DDR SDRAM applications.
·
1-to-10 Differential
Clock Distributions.
·
Low Skew (<100pS)
and Jitter (<100pS).
·
2.5V or 3.3V Vdda and
2.5V Vdd.
·
SSTL_2 level clock
inputs and outputs.
·
Low Current Power-Down
Modes.
·
Available in 48-pin
TSSOP Packages
DESCRIPTION
CB857 is a zero delay buffer
that distributes a SSTL_2 differential clock input pair to ten SSTL_2
differential pair of low-skew, low jitter clock outputs. It uses PLL to precisely
align, in both frequency and phase, the feedback clock outputs to the clock
input signal. Outputs are slope controlled, signal duty cycles are adjusted to
50%, independent of the duty cycle at clock input.
A CMOS style enable/disable
pin (PD*) is provided for power down mode. When PD* is low while power is
applied, the PLL is turned off and the differential clock outputs are 3-stated.
When the input frequency is less than approximately 20MHz, the device will
enter low power shut down mode. When the input frequency increases to greater
than approximately 20MHz, the PLL, and outputs will be enabled again. When VDDA
is grounded, the PLL is turned off and bypassed for test purposes.
FIG. 1. FUNCTIONAL BLOCK DIAGRAM