FEATURES
·
50% Duty Cycle Output
Optimized for registered DDR2 DIMM applications.
·
1-to-10 Differential
Clock Distributions.
·
Low Skew (<40pS) and
Jitter (<40pS).
·
1.8V or 2.5V Vdda and
Vdd.
·
LVCMOS level clock
inputs and outputs.
·
Low Current Power-Down
Modes.
·
Available in 40-pin MLF
& 52-Ball VF-BGA Packages
DESCRIPTION
CB877 is a zero delay buffer
that distributes a differential input clock pair CKIN/CKIN* to ten differential
output clock pairs Y[0:9]/Y[0:9]* and one differential feedback clock pair
FBOUT/FBOUT*. The output clocks are controlled by the input clock pair
CKIN/CKIN*, the feedback clock pair FBIN/FBIN*, the LVCMOS control inputs OE,
OS and the Analog Power input VDDA. When OE is Low, the outputs (except
FBOUT/FBOUT*) are disabled while the internal PLL continues to maintain its
locked-in frequency. OS (Output Select) is a program pin that must be tied to
VSS or VDD. When OS is High, OE will function as described above. When OS is
Low, OE has no effect on Y7/Y7* (they are free running in addition to
FBOUT/FBOUT*). When VDDA is grounded, the PLL is turned off and bypassed for
test purposes.
When both input clock
signals CKIN/CKIN* are logic Low, the device will enter a low power mode. An
input logic detection circuit on the differential inputs, independent from the
input buffer, will detect the logic Low level and perform a low power state
where all outputs, the feedback and the PLL are OFF. When inputs transition
from both being logic Low to being differential signals, the PLL will be turned
back on, the inputs and outputs will be enabled and the PLL will obtain phase
lock between the feedback clock pair FBIN/FBIN* and the input clock pair
CKIN/CKIN* within the specified stabilization time.
The PLL in the CB877 clock
driver uses the input clock CKIN/CKIN* and the feedback clocks FBIN/FBIN* to
provide high-performance, low-skew, low-jitter, nearly 50% duty cycle output
differential clocks Y[0:9]/Y[0:9]*. The CB877 is also able to track Spread
Spectrum Clocking (SSC) for reduced EMI.
PIN
ASSIGNMENT
BGA Topview
|
Y1 |
Y0 |
Y0* |
Y5* |
Y5 |
Y6 |
|
Y1* |
VSS |
VSS |
VSS |
VSS |
Y6* |
|
Y2* |
VSS |
NB |
NB |
VSS |
Y7* |
|
Y2 |
VDD |
VDD |
VDD |
OS |
Y7 |
|
CKIN |
VDD |
NB |
NB |
VDD |
FBIN |
|
CKIN* |
VDD |
NB |
NB |
OE |
FBIN* |
|
VSSA |
VDD |
VDD |
VDD |
VDD |
FBO* |
|
VDDA |
VSS |
NB |
NB |
VSS |
FBO |
|
Y3 |
VSS |
VSS |
VSS |
VSS |
Y8 |
|
Y3* |
Y4* |
Y4 |
Y9 |
Y9* |
Y8* |
52-Ball VF-BGA (10x6 Array,
7.0x4.5mm Body Size, 0.65mm Pitch, MO-225 Variation BA package pinouts.
