Synchronous Mode
Switching Regulator Controller
FEATURES
¨
Variable output 1.3V to
3.5V from 5V input
¨
85% efficiency or
better
¨
Frequency range from
200KHz to 1MHz
¨
Integrated Power Good
and Enable functions
¨
Internal Soft Start
Control
¨
Over-voltage protection
¨
Short circuit
protection with current limiting
¨
Drives N-channel
MOSFETs
¨
20 pin SOIC package
¨
Meets Intel Klamath
specifications
GENERAL
DESCRIPTION
The SR51 is a synchronous
mode switching regulator controller. It provides an accurate, variable output
voltage for all Pentium Pro CPU applications, including Klamath. The SR51 uses
a high level of integration to deliver load currents in excess of 15A from a 5V
source with minimal external circuitry. Using an integrated 5-bit D/A
converter, the output voltage may be selected from 1.3V to 3.5V.
Synchronous-mode operation offers optimum efficiency over the entire specified
output voltage range. The internal oscillator may be programmed from 200KHz to
1MHz for additional flexibility in choosing external components. An on board precision low TC reference
achieves tight tolerance voltage regulation without expensive external
components. The SR51 also offers integrated functions including Power Good,
Output Enable, Soft Start, over-voltage protection, and current limiting.
PIN
DEFINITIONS
|
Pin No |
Pin Name |
Type |
Descriptions |
|
1 |
CEXT |
A |
Connecting an external capacitor to this pin sets the
internal oscillator frequency. Layout of this pin is critical to system
performance. See Application Information for details. |
|
2 |
EN |
I |
A logic LOW on this pin will disable the output. An
internal pull-up resistor allows for either open collector or TTL
compatibility. |
|
3 |
PWGD |
OC |
An open collector output that will be at logic LOW if the
output voltage is not within ±12% of the
nominal output voltage set point. |
|
4 |
IFB |
A |
Pins 4 and 5 are used as the inputs for the current
feedback control loop. Layout of these traces is critical to system
performance. See Application Information for details. |
|
5 |
VFB |
A |
Pin 5 is used as the input for the voltage feedback
control loop and as the low side current feedback input. See Application Information for details
regarding correct layout. |
|
6 |
VDD |
P |
Connect to system 5V supply and de-coupled with a 0.1mF ceramic
capacitor. |
|
7 |
VDDP |
P |
Power input for low side FET driver connect to system 5V
supply and place a 4.7mF ceramic
capacitor. - To ground. |
|
8 |
VID4 |
I |
A logic 1 on this open collector/TTL input will enable the
VID3-VID0 inputs to set the output from 2.1V to 3.5V. A logic 0 will set the output from 1.3V to
2.05V. Pull-up resistors are internal
to the controller. |
|
9 |
DL |
O |
Low Side FET Driver connect this pin to the gate of an
N-channel MOSFET for synchronous operation.
The trace from this pin to the MOSFET gate should be < 0.5”. |
|
10, 11 |
VSSP |
P |
Return pin for high currents flowing in pins 7 and 13
(VDDP and VDDQ). Connect to a low
impedance ground. |
|
12 |
DH |
O |
High Side FET Driver connect this pin to the gate of an
N-channel MOSFET. The trace from this
pin to the MOSFET gate should be < 0.5” |
|
13 |
VDDQ |
P |
This is the supply for the high side FET driver. VDDQ
must be connected to a voltage of at least VDD + VGS, ON (MOSFET). |
|
14 |
VSS |
P |
Return path for digital logic. Connect to a low impedance system ground plane to minimize
ground loops. |
|
15 |
VSSA |
P |
Return path for low power analog circuitry. This pin should be connected to a low
impedance system ground plane to minimize ground loops. |
|
16 |
VREF |
A |
This pin provides access to the DAC output and should be
de-coupled to ground using 0.1mF capacitor. No load should be connected. |
|
17-20 |
VID0-VID3 |
I |
These open collector/TTL compatible inputs will set the
output voltage over the ranges specified in Table 1. Pull-up resistors are internal to the
controller. |
ELECTRICAL
SPECIFICATIONS
Absolute Maximum Ratings
|
Supply Voltages, Vddq |
13V |
|
Supply Voltage, Vdd, Vddp |
7V |
|
All Other Inputs |
7V |
|
Junction Temperature, TJ |
150°C |
|
Storage Temperature |
-65 to
150°C |
|
Lead Soldering Temperature, 10 seconds |
300°C |
Operating Conditions
|
Parameter |
Min. |
Typ. |
Max. |
Units |
Conditions |
|
Supply Voltage, Vdd, Vddp |
4.75 |
5 |
5.25 |
V |
VDD, VDDP pins |
|
Input Logic HIGH |
2.0 |
|
|
V |
All digital inputs |
|
Input Logic LOW |
|
|
0.8 |
V |
All digital inputs |
|
Ambient Operating Temp TA |
0 |
|
70 |
°C |
|
|
Output Driver Supply, Vddq |
8.5 |
|
12 |
V |
VDDQ pin |
|
PWGD threshold |
93 88 |
|
107 112 |
%VO %VO |
Logic High Logic Low |
DC, AC Characteristics
(Vdd=5V, VOUT=2.8V,
fOSC=300KHz, and TA=+25°C using circuit in Figure 1, unless otherwise noted)
The ¨ denotes specifications which apply over the full
operating temperature range.
|
Parameter |
Min |
Typ. |
Max. |
Units |
|
Conditions |
|
Output Voltage |
1.3 |
3.3 |
3.5 |
V |
¨ |
See Table 1 |
|
Output Current |
|
13 |
|
A |
|
|
|
Initial Voltage Set point |
|
±20 |
|
mV |
|
ILOAD=0.8A |
|
Output Temperature Drift |
|
+10 |
|
mV |
¨ |
TA=0
to 60°C |
|
Load Regulation |
|
-25 |
|
mV |
¨ |
ILOAD=0.8A
to 13A |
|
Line Regulation |
|
±11 |
|
mV |
¨ |
VIN=4.75V
to 5.25V |
|
Output Ripple |
|
±2 |
|
mV |
|
20MHz BW, ILOAD=13A
|
|
Output Voltage Regulation Steady State1 Transient2 |
2.74 2.66 |
2.80 2.80 |
2.90 2.94 |
V V |
¨ ¨ |
Vout=2.8V, ILOAD=0
to 13A ILOAD=0.8
to 13A, 30A/ms |
|
Output Voltage Regulation Steady State1 Transient2 |
1.74 1.70 |
1.80 1.80 |
1.90 1.90 |
V V |
¨ ¨ |
See Note 3 VOUT=1.8V ILOAD=0.8
to 11A, 30A/mS |
|
Efficiency |
80 |
85 |
|
% |
|