·
Stub-series
Terminated Logic for 2.5V Vddq.
·
Optimized for DDR
SDRAM Applications.
·
Supports SSTL_2
Signal Inputs and Outputs.
·
Flow-through Pin Out
Optimizes PCB Layout.
·
Meets SSTL_2 Class I
and Class II Specifications.
·
Latch-up Protections
Exceeds 100mA Per JESD78 ClassII.
·
ESD Protection
Exceeds JESD 22.
DESCRIPTION
The STL16857 is a 14-bit
SSTL_2 registered buffer with differential clock inputs. Both Vdd and Vddq
support 2.5V and 3.3V operation however. Vddq must not exceed Vdd. Inputs are
SSTL_2 type with Vref normally at Vddq/2. The outputs support class I which can
be used for standard stub-series applications or capacitive loads. Master reset
(RESET*) asynchronously resets all registers to zero.
The STL16857 is intended
to be incorporated into standard DIMM (Dual In-Line Memory Module) designs
defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory
Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both
clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR
DRAM rated at 100MHz will have a burst rate of 200MHz. The modules require
between 23 and 27 registered control and address lines, so two 14-bit wide
devices will be used on each module. The STL16857 is intended to be used for
SSTL_2 input and output signals.
The device data inputs
consist of differential receivers. One differential input is tied to the input
pin while the other is tied to a reference input pad, which is shared by all
inputs. When the reference input is left unconnected; an ½ Vdd voltage
reference will be automatically generated on chip.
The clock input is fully
differential to be compatible with DRAM device that are installed on the DIMM.
However, since the control inputs to the SDRAM change at only half the data
rate, the device must only change state on the positive transition of the CLK
signal. In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an asynchronous
input pin (reset, which when held to the LOW sate will assume that all
registers are reset to the LOW state and all outputs drive a LOW signal as
well.
FIG. 1. FUNCTIONAL BLOCK DIAGRAM