•  Differential ECL Inputs.
•  Regular & High Current Differential ECL Outputs.
•  Optimised Duty Cycle Skew Control.
•  100MHz High Speed Low Power Design.
•  Read/Write Control Registers.
•  100 Pin Plastic QFP Package.

This device provides ECL bus interface and data multiplexing functions for LAN Concentrators. A block diagram is shown in Figure 1. This device passes the input signals to output through an array of multiplexers. The control for the various multiplexers is accomplished by 8 internal registers. Four of these registers are 6-bit wide and four are 4-bit wide. These registers are readable and write accessible via the D<5-0> lines. They are addressed by A<2-0>.